Memory Map & Glue Logic

Memory Map

                      
                                 E000 - FFFF      ROM1     8K

                                 C000 - DFFF     ROM2     8K (not installed)

                                 8080 - BFFF      Not allocated

                                 8070 - 807F       Vacant

                                 8060 - 806F       Vacant

                                 8050 - 805F       Vacant

                                 8040 - 804F       Vacant

                                 8030 - 803F       Vacant

                                 8020 - 802F       6850 ACIA

                                 8010 - 801F         VIA

                                 8000 - 800F       LCD

                                 0000 - 7FFF       RAM       32K

The map itself may be less interesting that how I arrived at it so here is my reasoning:

• ROM must occupy the top of memory because the rest vectors reside at FFFA - FFFF
• I had a AT28C64 (8k) ROM I wanted to use so that had to go in at E000 - FFFF
• I had a 32k RAM.  Page zero and the stack reside in the bottom of memory so RAM must include at least 0000 - 01FF.  In practice this means RAM (32k) resides at 0000 - 7FFF
• That left  8000 - C000 so lots of space for IO so I left an option to add a second 8k ROM at C000 - DFFF.
• The challenge was then to design logic to select blocks of addresses for IO.  I studied what others had done and tried to learn.  Needless to say, I went through a lot of iterations with a pencil and paper but in the end I had something that looked ok, so I built it on breadboard to check it did what I expected.  This was a most useful exercise for learning about the glue logic generally and being sure it worked before a lot of soldering!  Although it took a few hours to assemble and thoroughly test, it was time very well spent.
• I decided I wanted blocks of 16 addresses for IO devices - 16 because that is the largest number of registers I could envisage for an IO device (my plan was to use a 6522 VIA that has 16 registers)
• A15 becomes the RAM select line (active low)
• By using 8000 - 8070 I could have 8 blocks of 16 addresses and all of them would be selected with A15 high and A7 - A14 low.

My design uses an 8 input OR gate to verify that A7 - A14 are all low.  The OR output drives an active low CS input on a 74LS138 3 to 8 decoder.  A15 drives an active high CS input.  That combination selects address 8000.  Address lines A4, A5 & A6 provide 8 combination that the 74LS138 IC decodes to set one of its outputs low.

Currently I am using three of those outputs and 5 are ready for further expansion

The ROM selection currently mirrors an 8k range of addresses but this is not a problem as my code uses E000 - FFFF only.  A planned extension is shown below in grey that selects one of two ROM chips.

This is how it looks:

I welcome critique and am hoping to see feedback on alternative approaches.  How did you do it?

Sure there are simpler solutions, but I think they 'waste' more addresses - that might not matter since they are not being used, but this was a learning exercise so wanted to find ways of achieving a specific set of objectives.

Lessons Learnt

• CMOS gates don't work - they are too slow.  I had lots of CD4000 series ICs and tried those first but soon discovered their limitations.
• Only PHI0 worked reliably - I tried PHI2 (honestly it was a wiring mistake!) but had erratic problems.  I think the WDC data sheet has something to say on this.  As long as I used PHI0 it worked fine
• Designing this stuff is conceptually straightforward but practically I found it difficult to get right.  Eventually I started writing truth tables and checking ALL logic states resulted in the required outputs - it is easy to overlook a combination!
• Building a breadboard version was incredibly helpful and exposed flaws in my logic