Experiments with 6522 VIA - Timers

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6522 VIA Timer 1 Free Running

This post covers my first exploration of the 6522 VIA.  The base system is a WDC65C02, 32K RAM, 8K ROM and a 16 x 2 line LCD display.

Objectives

  • Setup timer 1 in free-running mode
  • Begin to understand the capabilities and applications of a 6522 VIA
  • Try out interrupt generation and interrupt processing

Approach

The base system provided address decoding logic that allowed me to use a block of 16 addresses from $8010 to $801F to map onto the 16 registers of the 6522






This is how the device is connected into my 65C02 system:








Timers

There are two timers with slightly different features - in this post we'll look at Timer 1 in continuous or free running mode.  Timer 1 is a 16 bit counter that can operate in two modes - continuous or one-shot.  In continuous mode timing is:

      total cycles = n + 2         where n is the 16 bit value loaded

When the counter reaches zero the interrupt flag is set.

Here is a simple assembler program used to verify timings in continuous mode:

It is worth noting that clearing the interrupt flag takes a minimum of 11 clock cycles - 7 to prepare for the ISR and 4 for the LDA instruction that reads T1 counter low byte.  Depending on exactly when the interrupt occurs it may take longer because the 65C02 will complete the current instruction before commencing the ISR calling process.  In my code there is a JMP instruction in a tight loop that does nothing awaiting an interrupt so the worst case time to clear the interrupt is:

      complete JMP                                                 6 cycles
      set up ISR                                                       7 cycles
      LDA to read counter to clear interrupt flag    4 cycles
      TOTAL                                                         17 cycles

Result for Timer 1 - Continuous







Overall view of timings: IRQ is taken low at the end of each countdown.  PB7 toggles at the end each countdown also, generating a square wave.








More detail.  The number of cycles between IRQ going low and returning high is a minimum of 11 cycles but can take more depending on the current instruction. 











A closer view












Here we can see that the interrupt processing can take a different number of cycle








Conclusions

  • Timer 1 behaves as the datasheet describes
  • The shortest interval when using interrupts is 12 cycles since the minimum required to clear the interrupt flag is 11 cycles
  • PB7 can be used to generate a square wave

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